SPICE User's Guide |
Table of Contents |
| INTRODUCTION | CIRCUIT ELEMENTS AND MODELS | INTERACTIVE INTERPRETER | APPENDIX A |
| CIRCUIT DESCRIPTION | ANALYSES AND OUTPUT CONTROL | BIBLIOGRAPHY | APPENDIX B |
1. INTRODUCTION
SPICE is a general-purpose circuit simulation program
for nonlinear dc, nonlinear transient, and linear ac ana-
lyses. Circuits may contain resistors, capacitors, induc-
tors, mutual inductors, independent voltage and current
sources, four types of dependent sources, lossless and lossy
transmission lines (two separate implementations), switches,
uniform distributed RC lines, and the five most common sem-
iconductor devices: diodes, BJTs, JFETs, MESFETs, and MOS-
FETs.
The SPICE3 version is based directly on SPICE 2G.6.
While SPICE3 is being developed to include new features, it
continues to support those capabilities and models which
remain in extensive use in the SPICE2 program.
SPICE has built-in models for the semiconductor dev-
ices, and the user need specify only the pertinent model
parameter values. The model for the BJT is based on the
integral-charge model of Gummel and Poon; however, if the
Gummel- Poon parameters are not specified, the model reduces
to the simpler Ebers-Moll model. In either case, charge-
storage effects, ohmic resistances, and a current-dependent
output conductance may be included. The diode model can be
used for either junction diodes or Schottky barrier diodes.
The JFET model is based on the FET model of Shichman and
Hodges. Six MOSFET models are implemented: MOS1 is
described by a square-law I-V characteristic, MOS2 [1] is an
analytical model, while MOS3 [1] is a semi-empirical model;
MOS6 [2] is a simple analytic model accurate in the short-
channel region; MOS4 [3, 4] and MOS5 [5] are the BSIM
(Berkeley Short-channel IGFET Model) and BSIM2. MOS2, MOS3,
and MOS4 include second-order effects such as channel-length
modulation, subthreshold conduction, scattering-limited
velocity saturation, small-size effects, and charge-
controlled capacitances.
| TYPES OF ANALYSIS | ANALYSIS AT DIFFERENT TEMPERATURES | CONVERGENCE |
1.1. TYPES OF ANALYSIS
| DC Analysis | Transient Analysis | SmallSignal Distortion Analysis | Noise Analysis |
| AC SmallSignal Analysis | PoleZero Analysis | Sensitivity Analysis |
1.1.1. DC Analysis
The dc analysis portion of SPICE determines the dc
operating point of the circuit with inductors shorted and
capacitors opened. The dc analysis options are specified on
the .DC, .TF, and .OP control lines. A dc analysis is
automatically performed prior to a transient analysis to
determine the transient initial conditions, and prior to an
ac small-signal analysis to determine the linearized,
small-signal models for nonlinear devices. If requested,
the dc small-signal value of a transfer function (ratio of
output variable to input source), input resistance, and out-
put resistance is also computed as a part of the dc solu-
tion. The dc analysis can also be used to generate dc
transfer curves: a specified independent voltage or current
source is stepped over a user-specified range and the dc
output variables are stored for each sequential source
value.
1.1.2. AC Small-Signal Analysis
The ac small-signal portion of SPICE computes the ac
output variables as a function of frequency. The program
first computes the dc operating point of the circuit and
determines linearized, small-signal models for all of the
nonlinear devices in the circuit. The resultant linear cir-
cuit is then analyzed over a user-specified range of fre-
quencies. The desired output of an ac small- signal
analysis is usually a transfer function (voltage gain, tran-
simpedance, etc). If the circuit has only one ac input, it
is convenient to set that input to unity and zero phase, so
that output variables have the same value as the transfer
function of the output variable with respect to the input.
1.1.3. Transient Analysis
The transient analysis portion of SPICE computes the
transient output variables as a function of time over a
user-specified time interval. The initial conditions are
automatically determined by a dc analysis. All sources
which are not time dependent (for example, power supplies)
are set to their dc value. The transient time interval is
specified on a .TRAN control line.
1.1.4. Pole-Zero Analysis
The pole-zero analysis portion of SPICE computes the
poles and/or zeros in the small-signal ac transfer function.
The program first computes the dc operating point and then
determines the linearized, small-signal models for all the
nonlinear devices in the circuit. This circuit is then used
to find the poles and zeros of the transfer function.
Two types of transfer functions are allowed : one of
the form (output voltage)/(input voltage) and the other of
the form (output voltage)/(input current). These two types
of transfer functions cover all the cases and one can find
the poles/zeros of functions like input/output impedance and
voltage gain. The input and output ports are specified as
two pairs of nodes.
The pole-zero analysis works with resistors, capaci-
tors, inductors, linear-controlled sources, independent
sources, BJTs, MOSFETs, JFETs and diodes. Transmission
lines are not supported.
The method used in the analysis is a sub-optimal numer-
ical search. For large circuits it may take a considerable
time or fail to find all poles and zeros. For some cir-
cuits, the method becomes "lost" and finds an excessive
number of poles or zeros.
1.1.5. Small-Signal Distortion Analysis
The distortion analysis portion of SPICE computes
steady-state harmonic and intermodulation products for small
input signal magnitudes. If signals of a single frequency
are specified as the input to the circuit, the complex
values of the second and third harmonics are determined at
every point in the circuit. If there are signals of two
frequencies input to the circuit, the analysis finds out the
complex values of the circuit variables at the sum and
difference of the input frequencies, and at the difference
of the smaller frequency from the second harmonic of the
larger frequency.
Distortion analysis is supported for the following non-
linear devices: diodes (DIO), BJT, JFET, MOSFETs (levels 1,
2, 3, 4/BSIM1, 5/BSIM2, and 6) and MESFETS. All linear dev-
ices are automatically supported by distortion analysis. If
there are switches present in the circuit, the analysis con-
tinues to be accurate provided the switches do not change
state under the small excitations used for distortion calcu-
lations.
1.1.6. Sensitivity Analysis
Spice3 will calculate either the DC operating-point
sensitivity or the AC small-signal sensitivity of an output
variable with respect to all circuit variables, including
model parameters. Spice calculates the difference in an
output variable (either a node voltage or a branch current)
by perturbing each parameter of each device independently.
Since the method is a numerical approximation, the results
may demonstrate second order affects in highly sensitive
parameters, or may fail to show very low but non-zero sensi-
tivity. Further, since each variable is perturb by a small
fraction of its value, zero-valued parameters are not analy-
ized (this has the benefit of reducing what is usually a
very large amount of data).
1.1.7. Noise Analysis
The noise analysis portion of SPICE does analysis
device-generated noise for the given circuit. When provided
with an input source and an output port, the analysis calcu-
lates the noise contributions of each device (and each noise
generator within the device) to the output port voltage. It
also calculates the input noise to the circuit, equivalent
to the output noise referred to the specified input source.
This is done for every frequency point in a specified range
- the calculated value of the noise corresponds to the spec-
tral density of the circuit variable viewed as a stationary
gaussian stochastic process.
After calculating the spectral densities, noise
analysis integrates these values over the specified fre-
quency range to arrive at the total noise voltage/current
(over this frequency range). This calculated value
corresponds to the variance of the circuit variable viewed
as a stationary gaussian process.
1.2. ANALYSIS AT DIFFERENT TEMPERATURES
All input data for SPICE is assumed to have been meas-
o
ured at a nominal temperature of 27 C, which can be changed
by use of the TNOM parameter on the .OPTION control line.
This value can further be overridden for any device which
models temperature effects by specifying the TNOM parameter
on the model itself. The circuit simulation is performed at
o
a temperature of 27 C, unless overridden by a TEMP parameter
on the .OPTION control line. Individual instances may
further override the circuit temperature through the specif-
ication of a TEMP parameter on the instance.
Temperature dependent support is provided for resis-
tors, diodes, JFETs, BJTs, and level 1, 2, and 3 MOSFETs.
BSIM (levels 4 and 5) MOSFETs have an alternate temperature
dependency scheme which adjusts all of the model parameters
before input to SPICE. For details of the BSIM temperature
adjustment, see [6] and [7].
Temperature appears explicitly in the exponential terms
of the BJT and diode model equations. In addition, satura-
tion currents have a built-in temperature dependence. The
temperature dependence of the saturation current in the BJT
models is determined by:
XTI
|T | | E q(T T )|
1 g 1 0
I (T ) = I (T ) |--| exp|-----------|
S 1 S 0
|T | |k (T - T )|
0 1 0
where k is Boltzmann's constant, q is the electronic
charge, E is the energy gap which is a model parameter,
G
and XTI is the saturation current temperature exponent
(also a model parameter, and usually equal to 3).
The temperature dependence of forward and reverse beta
is according to the formula:
XTB
|T |
1
B(T ) = B(T ) |--|
1 0
|T |
0
where T and T are in degrees Kelvin, and XTB is a
1 0
user-supplied model parameter. Temperature effects on
beta are carried out by appropriate adjustment to the
values of B , I , B , and I (spice model parameters
F SE R SC
BF, ISE, BR, and ISC, respectively).
Temperature dependence of the saturation current in the
junction diode model is determined by:
XTI
---
N
|T | | E q(T T ) |
1 g 1 0
I (T ) = I (T ) |--| exp|-------------|
S 1 S 0
|T | |N k (T - T )|
0 1 0
where N is the emission coefficient, which is a model parameter, and the other symbols have the same meaning as above. Note that for Schottky barrier diodes, the value of the saturation current temperature exponent, XTI, is usually 2.
Temperature appears explicitly in the value of junction
potential, U (in spice PHI), for all the device models. The
temperature dependence is determined by:
| N N |
a d
kT |------ |
U(T) = -- log 2
q e |N (T) |
i
where k is Boltzmann's constant, q is the electronic
charge, N is the acceptor impurity density, N is the
a d
donor impurity density, N is the intrinsic carrier con-
i
centration, and E is the energy gap.
g
Temperature appears explicitly in the value of surface
mobility, M (or UO), for the MOSFET model. The temperature
0
dependence is determined by:
M (T )
0 0
M (T) = -------
0 1.5
| T|
|--|
|T |
0
The effects of temperature on resistors is modeled by
the formula:
2
R(T) = R(T ) [1 + TC (T - T ) + TC (T - T ) ]
0 1 0 2 0
where T is the circuit temperature, T is the nominal
0
temperature, and TC and TC are the first- and second-
1 2
order temperature coefficients.
1.3. CONVERGENCE
Both dc and transient solutions are obtained by an
iterative process which is terminated when both of the fol-
lowing conditions hold:
1) The nonlinear branch currents converge to within a
tolerance of 0.1% or 1 picoamp (1.0e-12 Amp), whichever
is larger.
2) The node voltages converge to within a tolerance of
0.1% or 1 microvolt (1.0e-6 Volt), whichever is larger.
Although the algorithm used in SPICE has been found to
be very reliable, in some cases it fails to converge to a
solution. When this failure occurs, the program terminates
the job.
Failure to converge in dc analysis is usually due to an
error in specifying circuit connections, element values, or
model parameter values. Regenerative switching circuits or
circuits with positive feedback probably will not converge
in the dc analysis unless the OFF option is used for some of
the devices in the feedback path, or the .NODESET control
line is used to force the circuit to converge to the desired
state.
2. CIRCUIT DESCRIPTION
| GENERAL STRUCTURE AND CONVENTIONS | DEVICE MODELS | COMBINING FILES | |
| TITLE LINE COMMENT LINES AND .END LINE | SUBCIRCUITS |
2.1. GENERAL STRUCTURE AND CONVENTIONS
The circuit to be analyzed is described to SPICE by a
set of element lines, which define the circuit topology and
element values, and a set of control lines, which define the
model parameters and the run controls. The first line in
the input file must be the title, and the last line must be
".END". The order of the remaining lines is arbitrary
(except, of course, that continuation lines must immediately
follow the line being continued).
Each element in the circuit is specified by an element
line that contains the element name, the circuit nodes to
which the element is connected, and the values of the param-
eters that determine the electrical characteristics of the
element. The first letter of the element name specifies the
element type. The format for the SPICE element types is
given in what follows. The strings XXXXXXX, YYYYYYY, and
ZZZZZZZ denote arbitrary alphanumeric strings. For example,
a resistor name must begin with the letter R and can contain
one or more characters. Hence, R, R1, RSE, ROUT, and
R3AC2ZY are valid resistor names. Details of each type of
device are supplied in a following section.
Fields on a line are separated by one or more blanks, a
comma, an equal ('=') sign, or a left or right parenthesis;
extra spaces are ignored. A line may be continued by enter-
ing a '+' (plus) in column 1 of the following line; SPICE
continues reading beginning with column 2.
A name field must begin with a letter (A through Z) and
cannot contain any delimiters.
A number field may be an integer field (12, -44), a
floating point field (3.14159), either an integer or float-
ing point number followed by an integer exponent (1e-14,
2.65e3), or either an integer or a floating point number
followed by one of the following scale factors:
12 9 6 3 -6
T = 10 G = 10 Meg = 10 K = 10 mil = 25.4
-3 -6 -9 -12 -15
m = 10 u (or M) = 10 n = 10 p = 10 f = 10
Letters immediately following a number that are not scale factors are ignored, and letters immediately following a scale factor are ignored. Hence, 10, 10V, 10Volts, and 10Hz all represent the same number, and M, MA, MSec, and MMhos all represent the same scale factor. Note that 1000, 1000.0, 1000Hz, 1e3, 1.0e3, 1KHz, and 1K all represent the same number.
Nodes names may be arbitrary character strings. The
datum (ground) node must be named '0'. Note the difference
in SPICE3 where the nodes are treated as character strings
and not evaluated as numbers, thus '0' and '00' are distinct
nodes in SPICE3 but not in SPICE2. The circuit cannot con-
tain a loop of voltage sources and/or inductors and cannot
contain a cut-set of current sources and/or capacitors.
Each node in the circuit must have a dc path to ground.
Every node must have at least two connections except for
transmission line nodes (to permit unterminated transmission
lines) and MOSFET substrate nodes (which have two internal
connections anyway).
2.2. TITLE LINE, COMMENT LINES AND .END LINE
| Title Line | .END Line | Comments |
2.2.1. Title Line
Examples:
POWER AMPLIFIER CIRCUIT
TEST OF CAM CELL
The title line must be the first in the input file.
Its contents are printed verbatim as the heading for each
section of output.
2.2.2. .END Line
Examples:
.END
The "End" line must always be the last in the input
file. Note that the period is an integral part of the
name.
2.2.3. Comments
General Form:
* <any comment>
Examples:
* RF=1K Gain should be 100
* Check open-loop gain and phase margin
The asterisk in the first column indicates that
this line is a comment line. Comment lines may be
placed anywhere in the circuit description. Note that
SPICE3 also considers any line with leading white space
to be a comment.
2.3. DEVICE MODELS
General form:
.MODEL MNAME TYPE(PNAME1=PVAL1 PNAME2=PVAL2 ... )
Examples:
.MODEL MOD1 NPN (BF=50 IS=1E-13 VBF=50)
Most simple circuit elements typically require only a
few parameter values. However, some devices (semiconductor
devices in particular) that are included in SPICE require
many parameter values. Often, many devices in a circuit are
defined by the same set of device model parameters. For
these reasons, a set of device model parameters is defined
on a separate .MODEL line and assigned a unique model name.
The device element lines in SPICE then refer to the model
name.
For these more complex device types, each device ele-
ment line contains the device name, the nodes to which the
device is connected, and the device model name. In addi-
tion, other optional parameters may be specified for some
devices: geometric factors and an initial condition (see
the following section on Transistors and Diodes for more de-
tails).
MNAME in the above is the model name, and type is one
of the following fifteen types:
R Semiconductor resistor model
C Semiconductor capacitor model
SW Voltage controlled switch
CSW Current controlled switch
URC Uniform distributed RC model
LTRA Lossy transmission line model
D Diode model
NPN NPN BJT model
PNP PNP BJT model
NJF N-channel JFET model
PJF P-channel JFET model
NMOS N-channel MOSFET model
PMOS P-channel MOSFET model
NMF N-channel MESFET model
PMF P-channel MESFET model
Parameter values are defined by appending the parameter
name followed by an equal sign and the parameter value.
Model parameters that are not given a value are assigned the
default values given below for each model type. Models,
model parameters, and default values are listed in the next
section along with the description of device element lines.
2.4. SUBCIRCUITS
A subcircuit that consists of SPICE elements can be
defined and referenced in a fashion similar to device
models. The subcircuit is defined in the input file by a
grouping of element lines; the program then automatically
inserts the group of elements wherever the subcircuit is
referenced. There is no limit on the size or complexity of
subcircuits, and subcircuits may contain other subcircuits.
An example of subcircuit usage is given in Appendix A.
| .SUBCKT Line | .ENDS Line | Subcircuit Calls |
2.4.1. .SUBCKT Line
General form:
.SUBCKT subnam N1 <N2 N3 ...>
Examples:
.SUBCKT OPAMP 1 2 3 4
A circuit definition is begun with a .SUBCKT line.
SUBNAM is the subcircuit name, and N1, N2, ... are the
external nodes, which cannot be zero. The group of element
lines which immediately follow the .SUBCKT line define the
subcircuit. The last line in a subcircuit definition is the
.ENDS line (see below). Control lines may not appear within
a subcircuit definition; however, subcircuit definitions
may contain anything else, including other subcircuit defin-
itions, device models, and subcircuit calls (see below).
Note that any device models or subcircuit definitions
included as part of a subcircuit definition are strictly
local (i.e., such models and definitions are not known out-
side the subcircuit definition). Also, any element nodes
not included on the .SUBCKT line are strictly local, with
the exception of 0 (ground) which is always global.
2.4.2. .ENDS Line
General form:
.ENDS <SUBNAM>
Examples:
.ENDS OPAMP
The "Ends" line must be the last one for any sub-
circuit definition. The subcircuit name, if included,
indicates which subcircuit definition is being terminat-
ed; if omitted, all subcircuits being defined are ter-
minated. The name is needed only when nested subcircuit
definitions are being made.
2.4.3. Subcircuit Calls
General form:
XYYYYYYY N1 <N2 N3 ...> SUBNAM
Examples:
X1 2 4 17 3 1 MULTI
Subcircuits are used in SPICE by specifying
pseudo-elements beginning with the letter X, followed by
the circuit nodes to be used in expanding the subcir-
cuit.
2.5. COMBINING FILES: .INCLUDE LINES
General form:
.INCLUDE filename
Examples:
.INCLUDE /users/spice/common/wattmeter.cir
Frequently, portions of circuit descriptions will be
reused in several input files, particularly with common
models and subcircuits. In any spice input file, the
".include" line may be used to copy some other file as if
that second file appeared in place of the ".include" line in
the original file. There is no restriction on the file name
imposed by spice beyond those imposed by the local operating
system.
3. CIRCUIT ELEMENTS AND MODELS
Data fields that are enclosed in less-than and
greater-than signs ('< >') are optional. All indicated
punctuation (parentheses, equal signs, etc.) is optional but
indicate the presence of any delimiter. Further, future
implementations may require the punctuation as stated. A
consistent style adhering to the punctuation shown here
makes the input easier to understand. With respect to
branch voltages and currents, SPICE uniformly uses the asso-
ciated reference convention (current flows in the direction
of voltage drop).
| ELEMENTARY DEVICES | VOLTAGE AND CURRENT SOURCES | TRANSMISSION LINES | TRANSISTORS AND DIODES |
3.1. ELEMENTARY DEVICES
| Resistors | Capacitors | Inductors | Switch Model |
| Semiconductor Resistors | Semiconductor Capacitors | Coupled Inductors | |
| Semiconductor Resistor Model | Semiconductor Capacitor Model | Switches |
3.1.1. Resistors
General form:
RXXXXXXX N1 N2 VALUE
Examples:
R1 1 2 100
RC1 12 17 1K
N1 and N2 are the two element nodes. VALUE is the
resistance (in ohms) and may be positive or negative but not
zero.
3.1.2. Semiconductor Resistors
General form:
RXXXXXXX N1 N2 <VALUE> <MNAME> <L=LENGTH> <W=WIDTH> <TEMP=T>
Examples:
RLOAD 2 10 10K
RMOD 3 7 RMODEL L=10u W=1u
This is the more general form of the resistor presented
in section 6.1, and allows the modeling of temperature
effects and for the calculation of the actual resistance
value from strictly geometric information and the specifica-
tions of the process. If VALUE is specified, it overrides
the geometric information and defines the resistance. If
MNAME is specified, then the resistance may be calculated
from the process information in the model MNAME and the
given LENGTH and WIDTH. If VALUE is not specified, then
MNAME and LENGTH must be specified. If WIDTH is not speci-
fied, then it is taken from the default width given in the
model. The (optional) TEMP value is the temperature at
which this device is to operate, and overrides the tempera-
ture specification on the .OPTION control line.
3.1.3. Semiconductor Resistor Model (R)
The resistor model consists of process-related device
data that allow the resistance to be calculated from
geometric information and to be corrected for temperature.
The parameters available are:
name parameter units default example
o
TC1 first order temperature coeff. Z/ C 0.0 -
o 2
TC2 second order temperature coeff. Z/ C 0.0 -
RSH sheet resistance Z/[] - 50
DEFW default width meters 1e-6 2e-6
NARROW narrowing due to side etching meters 0.0 1e-7
o
TNOM parameter measurement temperature C 27 50
The sheet resistance is used with the narrowing parame-
ter and L and W from the resistor device to determine the
nominal resistance by the formula
L - NARROW
R = RSH ----------
W - NARROW
DEFW is used to supply a default value for W if one is not specified for the device. If either RSH or L is not speci- fied, then the standard default resistance value of 1k Z is used. TNOM is used to override the circuit-wide value given on the .OPTIONS control line where the parameters of this model have been measured at a different temperature. After the nominal resistance is calculated, it is adjusted for temperature by the formula:
2
R(T) = R(T ) [1 + TC1 (T - T ) + TC2 (T-T ) ]
0 0 0
3.1.4. Capacitors
General form:
CXXXXXXX N+ N- VALUE <IC=INCOND>
Examples:
CBYP 13 0 1UF
COSC 17 23 10U IC=3V
N+ and N- are the positive and negative element
nodes, respectively. VALUE is the capacitance in
Farads.
The (optional) initial condition is the initial (time-
zero) value of capacitor voltage (in Volts). Note that the
initial conditions (if any) apply 'only' if the UIC option
is specified on the .TRAN control line.
3.1.5. Semiconductor Capacitors
General form:
CXXXXXXX N1 N2 <VALUE> <MNAME> <L=LENGTH> <W=WIDTH> <IC=VAL>
Examples:
CLOAD 2 10 10P
CMOD 3 7 CMODEL L=10u W=1u
This is the more general form of the Capacitor
presented in section 6.2, and allows for the calculation of
the actual capacitance value from strictly geometric infor-
mation and the specifications of the process. If VALUE is
specified, it defines the capacitance. If MNAME is speci-
fied, then the capacitance is calculated from the process
information in the model MNAME and the given LENGTH and
WIDTH. If VALUE is not specified, then MNAME and LENGTH
must be specified. If WIDTH is not specified, then it is
taken from the default width given in the model. Either
VALUE or MNAME, LENGTH, and WIDTH may be specified, but not
both sets.
3.1.6. Semiconductor Capacitor Model (C)
The capacitor model contains process information that
may be used to compute the capacitance from strictly
geometric information.
name parameter units default example
2
CJ junction bottom capacitance F/meters - 5e-5
CJSW junction sidewall capacitance F/meters - 2e-11
DEFW default device width meters 1e-6 2e-6
NARROW narrowing due to side etching meters 0.0 1e-7
The capacitor has a capacitance computed as
CAP = CJ (LENGTH - NARROW) (WIDTH - NARROW) + 2 CJSW (LENGTH + WIDTH - 2 NARROW)
3.1.7. Inductors
General form:
LYYYYYYY N+ N- VALUE <IC=INCOND>
Examples:
LLINK 42 69 1UH
LSHUNT 23 51 10U IC=15.7MA
N+ and N- are the positive and negative element
nodes, respectively. VALUE is the inductance in Hen-
ries.
The (optional) initial condition is the initial (time-
zero) value of inductor current (in Amps) that flows from
N+, through the inductor, to N-. Note that the initial con-
ditions (if any) apply only if the UIC option is specified
on the .TRAN analysis line.
3.1.8. Coupled (Mutual) Inductors
General form:
KXXXXXXX LYYYYYYY LZZZZZZZ VALUE
Examples:
K43 LAA LBB 0.999
KXFRMR L1 L2 0.87
LYYYYYYY and LZZZZZZZ are the names of the two cou-
pled inductors, and VALUE is the coefficient of cou-
pling, K, which must be greater than 0 and less than or
equal to 1. Using the 'dot' convention, place a 'dot'
on the first node of each inductor.
3.1.9. Switches
General form:
SXXXXXXX N+ N- NC+ NC- MODEL <ON><OFF>
WYYYYYYY N+ N- VNAM MODEL <ON><OFF>
Examples:
s1 1 2 3 4 switch1 ON
s2 5 6 3 0 sm2 off
Switch1 1 2 10 0 smodel1
w1 1 2 vclock switchmod1
W2 3 0 vramp sm1 ON
wreset 5 6 vclck lossyswitch OFF
Nodes 1 and 2 are the nodes between which the
switch terminals are connected. The model name is man-
datory while the initial conditions are optional. For
the voltage controlled switch, nodes 3 and 4 are the po-
sitive and negative controlling nodes respectively. For
the current controlled switch, the controlling current
is that through the specified voltage source. The
direction of positive controlling current flow is from
the positive node, through the source, to the negative
node.
3.1.10. Switch Model (SW/CSW)
The switch model allows an almost ideal switch to be
described in SPICE. The switch is not quite ideal, in that
the resistance can not change from 0 to infinity, but must
always have a finite positive value. By proper selection of
the on and off resistances, they can be effectively zero and
infinity in comparison to other circuit elements. The
parameters available are:
name parameter units default switch
VT threshold voltage Volts 0.0 S
IT threshold current Amps 0.0 W
VH hysteresis voltage Volts 0.0 S
IH hysteresis current Amps 0.0 W
RON on resistance Z 1.0 both
ROFF off resistance Z 1/GMIN* both
*(See the .OPTIONS control line for a description of
GMIN, its default value results in an off-resistance of
1.0e+12 ohms.)
The use of an ideal element that is highly nonlinear
such as a switch can cause large discontinuities to occur in
the circuit node voltages. A rapid change such as that
associated with a switch changing state can cause numerical
roundoff or tolerance problems leading to erroneous results
or timestep difficulties. The user of switches can improve
the situation by taking the following steps:
First, it is wise to set ideal switch impedances just
high or low enough to be negligible with respect to other
circuit elements. Using switch impedances that are close to
"ideal" in all cases aggravates the problem of discontinui-
ties mentioned above. Of course, when modeling real devices
such as MOSFETS, the on resistance should be adjusted to a
realistic level depending on the size of the device being
modeled.
If a wide range of ON to OFF resistance must be used in
the switches (ROFF/RON >1e+12), then the tolerance on errors
allowed during transient analysis should be decreased by
using the .OPTIONS control line and specifying TRTOL to be
less than the default value of 7.0. When switches are
placed around capacitors, then the option CHGTOL should also
be reduced. Suggested values for these two options are 1.0
and 1e-16 respectively. These changes inform SPICE3 to be
more careful around the switch points so that no errors are
made due to the rapid change in the circuit.
3.2. VOLTAGE AND CURRENT SOURCES
| Independent Sources | Linear Dependent Sources | Nonlinear Dependent Sources |
3.2.1. Independent Sources
General form:
VXXXXXXX N+ N- <<DC> DC/TRAN VALUE> <AC <ACMAG <ACPHASE>>>
+ <DISTOF1 <F1MAG <F1PHASE>>> <DISTOF2 <F2MAG <F2PHASE>>>
IYYYYYYY N+ N- <<DC> DC/TRAN VALUE> <AC <ACMAG <ACPHASE>>>
+ <DISTOF1 <F1MAG <F1PHASE>>> <DISTOF2 <F2MAG <F2PHASE>>>
Examples:
VCC 10 0 DC 6
VIN 13 2 0.001 AC 1 SIN(0 1 1MEG)
ISRC 23 21 AC 0.333 45.0 SFFM(0 1 10K 5 1K)
VMEAS 12 9
VCARRIER 1 0 DISTOF1 0.1 -90.0
VMODULATOR 2 0 DISTOF2 0.01
IIN1 1 5 AC 1 DISTOF1 DISTOF2 0.001
N+ and N- are the positive and negative nodes, respec-
tively. Note that voltage sources need not be grounded.
Positive current is assumed to flow from the positive node,
through the source, to the negative node. A current source
of positive value forces current to flow out of the N+ node,
through the source, and into the N- node. Voltage sources,
in addition to being used for circuit excitation, are the
'ammeters' for SPICE, that is, zero valued voltage sources
may be inserted into the circuit for the purpose of measur-
ing current. They of course have no effect on circuit
operation since they represent short-circuits.
DC/TRAN is the dc and transient analysis value of the
source. If the source value is zero both for dc and tran-
sient analyses, this value may be omitted. If the source
value is time-invariant (e.g., a power supply), then the
value may optionally be preceded by the letters DC.
ACMAG is the ac magnitude and ACPHASE is the ac phase.
The source is set to this value in the ac analysis. If
ACMAG is omitted following the keyword AC, a value of unity
is assumed. If ACPHASE is omitted, a value of zero is
assumed. If the source is not an ac small-signal input, the
keyword AC and the ac values are omitted.
DISTOF1 and DISTOF2 are the keywords that specify that
the independent source has distortion inputs at the frequen-
cies F1 and F2 respectively (see the description of the
.DISTO control line). The keywords may be followed by an
optional magnitude and phase. The default values of the
magnitude and phase are 1.0 and 0.0 respectively.
Any independent source can be assigned a time-dependent
value for transient analysis. If a source is assigned a
time-dependent value, the time-zero value is used for dc
analysis. There are five independent source functions:
pulse, exponential, sinusoidal, piece-wise linear, and
single-frequency FM. If parameters other than source values
are omitted or set to zero, the default values shown are
assumed. (TSTEP is the printing increment and TSTOP is the
final time (see the .TRAN control line for explanation)).
| Pulse | Exponential | SingleFrequency FM | |
| Sinusoidal | PieceWise Linear |
3.2.1.1. Pulse
General form:
PULSE(V1 V2 TD TR TF PW PER)
Examples:
VIN 3 0 PULSE(-1 1 2NS 2NS 2NS 50NS 100NS)
parameter default value units
-----------------------------------------------------
V1 (initial value) Volts or Amps
V2 (pulsed value) Volts or Amps
TD (delay time) 0.0 seconds
TR (rise time) TSTEP seconds
TF (fall time) TSTEP seconds
PW (pulse width) TSTOP seconds
PER(period) TSTOP seconds
A single pulse so specified is described by the follow-
ing table:
time value
-------------------
0 V1
TD V1
TD+TR V2
TD+TR+PW V2
TD+TR+PW+TF V1
TSTOP V1
Intermediate points are determined by linear interpola-
tion.
3.2.1.2. Sinusoidal
General form:
SIN(VO VA FREQ TD THETA)
Examples:
VIN 3 0 SIN(0 1 100MEG 1NS 1E10)
parameters default value units
-------------------------------------------------------
VO (offset) Volts or Amps
VA (amplitude) Volts or Amps
FREQ (frequency) 1/TSTOP Hz
TD (delay) 0.0 seconds
THETA (damping factor) 0.0 1/seconds
The shape of the waveform is described by the following
table:
time value
------------------------------------------------------------
0 to TD VO
-(t - TD)THETA
TD to TSTOP VO + VA e sin(2 J FREQ (t + TD))
3.2.1.3. Exponential
General Form:
EXP(V1 V2 TD1 TAU1 TD2 TAU2)
Examples:
VIN 3 0 EXP(-4 -1 2NS 30NS 60NS 40NS)
parameter default value units
---------------------------------------------------------
V1 (initial value) Volts or Amps
V2 (pulsed value) Volts or Amps
TD1 (rise delay time) 0.0 seconds
TAU1 (rise time constant) TSTEP seconds
TD2 (fall delay time) TD1+TSTEP seconds
TAU2 (fall time constant) TSTEP seconds
The shape of the waveform is described by the following
table:
time value
----------------------------------------------------------------------------
0 to TD1 V1
| ------------|
TAU1
| -(t - TD1) | -(t - TD2)
TD1 to TD2 V1 + (V2 - V1) 1 - e
| ----------| | ----------|
| TAU1 | | TAU2 |
TD2 to TSTOP V1 + (V2 - V1) - e + (V1 - V2) 1 - e
3.2.1.4. Piece-Wise Linear
General Form:
PWL(T1 V1 <T2 V2 T3 V3 T4 V4 ...>)
Examples:
VCLOCK 7 5 PWL(0 -7 10NS -7 11NS -3 17NS -3 18NS -7 50NS -7)
Each pair of values (Ti, Vi) specifies that the value
of the source is Vi (in Volts or Amps) at time=Ti. The
value of the source at intermediate values of time is deter-
mined by using linear interpolation on the input values.
3.2.1.5. Single-Frequency FM
General Form:
SFFM(VO VA FC MDI FS)
Examples:
V1 12 0 SFFM(0 1M 20K 5 1K)
parameter default value units
-------------------------------------------------------
VO (offset) Volts or Amps
VA (amplitude) Volts or Amps
FC (carrier frequency) 1/TSTOP Hz
MDI (modulation index)
FS (signal frequency) 1/TSTOP Hz
The shape of the waveform is described by the following equation:
| |
V(t)=V + V sin 2 J FC t + MDI sin(2 J FS t)
O A | |
3.2.2. Linear Dependent Sources
SPICE allows circuits to contain linear dependent
sources characterized by any of the four equations
i = g v v = e v i = f i v
= h i
where g, e, f, and h are constants representing transconduc- tance, voltage gain, current gain, and transresistance, respectively.
| Linear VoltageControlled Current Sources | Linear VoltageControlled Voltage Sources | Linear CurrentControlled Current Sources | Linear CurrentControlled Voltage Sources |
3.2.2.1. Linear Voltage-Controlled Current Sources
General form:
GXXXXXXX N+ N- NC+ NC- VALUE
Examples:
G1 2 0 5 0 0.1MMHO
N+ and N- are the positive and negative nodes,
respectively. Current flow is from the positive node,
through the source, to the negative node. NC+ and NC-
are the positive and negative controlling nodes, respec-
tively. VALUE is the transconductance (in mhos).
3.2.2.2. Linear Voltage-Controlled Voltage Sources
General form:
EXXXXXXX N+ N- NC+ NC- VALUE
Examples:
E1 2 3 14 1 2.0
N+ is the positive node, and N- is the negative
node. NC+ and NC- are the positive and negative con-
trolling nodes, respectively. VALUE is the voltage
gain.
3.2.2.3. Linear Current-Controlled Current Sources
General form:
FXXXXXXX N+ N- VNAM VALUE
Examples:
F1 13 5 VSENS 5
N+ and N- are the positive and negative nodes,
respectively. Current flow is from the positive node,
through the source, to the negative node. VNAM is the
name of a voltage source through which the controlling
current flows. The direction of positive controlling
current flow is from the positive node, through the
source, to the negative node of VNAM. VALUE is the
current gain.
3.2.2.4. Linear Current-Controlled Voltage Sources
General form:
HXXXXXXX N+ N- VNAM VALUE
Examples:
HX 5 17 VZ 0.5K
N+ and N- are the positive and negative nodes,
respectively. VNAM is the name of a voltage source
through which the controlling current flows. The direc-
tion of positive controlling current flow is from the
positive node, through the source, to the negative node
of VNAM. VALUE is the transresistance (in ohms).
3.2.3. Non-linear Dependent Sources
General form:
BXXXXXXX N+ N- <I=EXPR> <V=EXPR>
Examples:
B1 0 1 I=cos(v(1))+sin(v(2))
B1 0 1 V=ln(cos(log(v(1,2)^2)))-v(3)^4+v(2)^v(1)
B1 3 4 I=17
B1 3 4 V=exp(pi^i(vdd))
N+ is the positive node, and N- is the negative node.
The values of the V and I parameters determine the voltages
and currents across and through the device, respectively.
If I is given then the device is a current source, and if V
is given the device is a voltage source. One and only one
of these parameters must be given.
The small-signal AC behavior of the nonlinear source is
a linear dependent source (or sources) with a proportional-
ity constant equal to the derivative (or derivatives) of the
source at the DC operating point.
The expressions given for V and I may be any function
of voltages and currents through voltage sources in the sys-
tem. The following functions of real variables are defined:
abs asinh cosh sin
acos atan exp sinh
acosh atanh ln sqrt
asin cos log tan
The function "u" is the unit step function, with a
value of one for arguments greater than one and a value of
zero for arguments less than zero. The function "uramp" is
the integral of the unit step: for an input x, the value is
zero if x is less than zero, or if x is greater than zero
the value is x. These two functions are useful in sythesiz-
ing piece-wise non-linear functions, though convergence may
be adversely affected.
The following standard operators are defined:
+ - * / ^ unary -
If the argument of log, ln, or sqrt becomes less than
zero, the absolute value of the argument is used. If a
divisor becomes zero or the argument of log or ln becomes
zero, an error will result. Other problems may occur when
the argument for a function in a partial derivative enters a
region where that function is undefined.
To get time into the expression you can integrate the
current from a constant current source with a capacitor and
use the resulting voltage (don't forget to set the initial
voltage across the capacitor). Non-linear resistors, capa-
citors, and inductors may be synthesized with the nonlinear
dependent source. Non-linear resistors are obvious. Non-
linear capacitors and inductors are implemented with their
linear counterparts by a change of variables implemented
with the nonlinear dependent source. The following subcir-
cuit will implement a nonlinear capacitor:
.Subckt nlcap pos neg
* Bx: calculate f(input voltage)
Bx 1 0 v = f(v(pos,neg))
* Cx: linear capacitance
Cx 2 0 1
* Vx: Ammeter to measure current into the capacitor
Vx 2 1 DC 0Volts
* Drive the current through Cx back into the circuit
Fx pos neg Vx 1
.ends
Non-linear inductors are similar.
3.3. TRANSMISSION LINES
| Lossless Transmission Lines | Lossy Transmission Line Model | Uniform Distributed RC Model | |
| Lossy Transmission Lines | Uniform Distributed RC Lines |
3.3.1. Lossless Transmission Lines
General form:
TXXXXXXX N1 N2 N3 N4 Z0=VALUE <TD=VALUE> <F=FREQ <NL=NRMLEN>>
+ <IC=V1, I1, V2, I2>
Examples:
T1 1 0 2 0 Z0=50 TD=10NS
N1 and N2 are the nodes at port 1; N3 and N4 are the
nodes at port 2. Z0 is the characteristic impedance. The
length of the line may be expressed in either of two forms.
The transmission delay, TD, may be specified directly (as
TD=10ns, for example). Alternatively, a frequency F may be
given, together with NL, the normalized electrical length of
the transmission line with respect to the wavelength in the
line at the frequency F. If a frequency is specified but NL
is omitted, 0.25 is assumed (that is, the frequency is
assumed to be the quarter-wave frequency). Note that
although both forms for expressing the line length are indi-
cated as optional, one of the two must be specified.
Note that this element models only one propagating
mode. If all four nodes are distinct in the actual circuit,
then two modes may be excited. To simulate such a situa-
tion, two transmission-line elements are required. (see the
example in Appendix A for further clarification.)
The (optional) initial condition specification consists
of the voltage and current at each of the transmission line
ports. Note that the initial conditions (if any) apply
'only' if the UIC option is specified on the .TRAN control
line.
Note that a lossy transmission line (see below) with
zero loss may be more accurate than than the lossless
transmission line due to implementation details.
3.3.2. Lossy Transmission Lines
General form:
OXXXXXXX N1 N2 N3 N4 MNAME
Examples:
O23 1 0 2 0 LOSSYMOD
OCONNECT 10 5 20 5 INTERCONNECT
This is a two-port convolution model for single-
conductor lossy transmission lines. N1 and N2 are the nodes
at port 1; N3 and N4 are the nodes at port 2. Note that a
lossy transmission line with zero loss may be more accurate
than than the lossless transmission line due to implementa-
tion details.
3.3.3. Lossy Transmission Line Model (LTRA)
The uniform RLC/RC/LC/RG transmission line model (re-
ferred to as the LTRA model henceforth) models a uniform
constant-parameter distributed transmission line. The RC
and LC cases may also be modeled using the URC and TRA
models; however, the newer LTRA model is usually faster and
more accurate than the others. The operation of the LTRA
model is based on the convolution of the transmission line's
impulse responses with its inputs (see [8]).
The LTRA model takes a number of parameters, some of
which must be given and some of which are optional.
name parameter units/type default example
R resistance/length Z/unit 0.0 0.2
L inductance/length henrys/unit 0.0 9.13e-9
G conductance/length mhos/unit 0.0 0.0
C capacitance/length farads/unit 0.0 3.65e-12
LEN length of line no default 1.0
REL breakpoint control arbitrary unit 1 0.5
ABS breakpoint control 1 5
NOSTEPLIMIT don't limit timestep to less than flag not set set
line delay
NOCONTROL don't do complex timestep control flag not set set
LININTERP use linear interpolation flag not set set
MIXEDINTERP use linear when quadratic seems bad not set set
COMPACTREL special reltol for history compaction flag RELTOL 1.0e-3
COMPACTABS special abstol for history compaction ABSTOL 1.0e-9
TRUNCNR use Newton-Raphson method for flag not set set
timestep control
TRUNCDONTCUT don't limit timestep to keep flag not set set
impulse-response errors low
The following types of lines have been implemented so
far: RLC (uniform transmission line with series loss only),
RC (uniform RC line), LC (lossless transmission line), and
RG (distributed series resistance and parallel conductance
only). Any other combination will yield erroneous results
and should not be tried. The length LEN of the line must be
specified.
NOSTEPLIMIT is a flag that will remove the default res-
triction of limiting time-steps to less than the line delay
in the RLC case. NOCONTROL is a flag that prevents the
default limiting of the time-step based on convolution error
criteria in the RLC and RC cases. This speeds up simulation
but may in some cases reduce the accuracy of results.
LININTERP is a flag that, when specified, will use linear
interpolation instead of the default quadratic interpolation
for calculating delayed signals. MIXEDINTERP is a flag
that, when specified, uses a metric for judging whether qua-
dratic interpolation is not applicable and if so uses linear
interpolation; otherwise it uses the default quadratic
interpolation. TRUNCDONTCUT is a flag that removes the
default cutting of the time-step to limit errors in the
actual calculation of impulse-response related quantities.
COMPACTREL and COMPACTABS are quantities that control the
compaction of the past history of values stored for convolu-
tion. Larger values of these lower accuracy but usually
increase simulation speed. These are to be used with the
TRYTOCOMPACT option, described in the .OPTIONS section.
TRUNCNR is a flag that turns on the use of Newton-Raphson
iterations to determine an appropriate timestep in the
timestep control routines. The default is a trial and error
procedure by cutting the previous timestep in half. REL and
ABS are quantities that control the setting of breakpoints.
The option most worth experimenting with for increasing
the speed of simulation is REL. The default value of 1 is
usually safe from the point of view of accuracy but occa-
sionally increases computation time. A value greater than 2
eliminates all breakpoints and may be worth trying depending
on the nature of the rest of the circuit, keeping in mind
that it might not be safe from the viewpoint of accuracy.
Breakpoints may usually be entirely eliminated if it is
expected the circuit will not display sharp discontinuities.
Values between 0 and 1 are usually not required but may be
used for setting many breakpoints.
COMPACTREL may also be experimented with when the
option TRYTOCOMPACT is specified in a .OPTIONS card. The
legal range is between 0 and 1. Larger values usually
decrease the accuracy of the simulation but in some cases
improve speed. If TRYTOCOMPACT is not specified on a
.OPTIONS card, history compaction is not attempted and accu-
racy is high. NOCONTROL, TRUNCDONTCUT and NOSTEPLIMIT also
tend to increase speed at the expense of accuracy.
3.3.4. Uniform Distributed RC Lines (Lossy)
General form:
UXXXXXXX N1 N2 N3 MNAME L=LEN <N=LUMPS>
Examples:
U1 1 2 0 URCMOD L=50U
URC2 1 12 2 UMODL l=1MIL N=6
N1 and N2 are the two element nodes the RC line con-
nects, while N3 is the node to which the capacitances are
connected. MNAME is the model name, LEN is the length of
the RC line in meters. LUMPS, if specified, is the number
of lumped segments to use in modeling the RC line (see the
model description for the action taken if this parameter is
omitted).
3.3.5. Uniform Distributed RC Model (URC)
The URC model is derived from a model proposed by L.
Gertzberrg in 1974. The model is accomplished by a subcir-
cuit type expansion of the URC line into a network of lumped
RC segments with internally generated nodes. The RC seg-
ments are in a geometric progression, increasing toward the
middle of the URC line, with K as a proportionality con-
stant. The number of lumped segments used, if not specified
for the URC line device, is determined by the following for-
mula:
2
| R C |(K-1)| |
_ _ 2
log|F 2 J L |-----| |
max
| L L | K | |
N = ------------------------------
log K
The URC line is made up strictly of resistor and capa-
citor segments unless the ISPERL parameter is given a non-
zero value, in which case the capacitors are replaced with
reverse biased diodes with a zero-bias junction capacitance
equivalent to the capacitance replaced, and with a satura-
tion current of ISPERL amps per meter of transmission line
and an optional series resistance equivalent to RSPERL ohms
per meter.
name parameter units default example area
1 K Propagation Constant - 2.0 1.2 - 2 FMAX Maximum Frequency of interest Hz 1.0G 6.5Meg - 3 RPERL Resistance per unit length Z/m 1000 10 - 4 CPERL Capacitance per unit length F/m 1.0e-15 1pF - 5 ISPERL Saturation Current per unit length A/m 0 - - 6 RSPERL Diode Resistance per unit length Z/m 0 - -
3.4. TRANSISTORS AND DIODES
The area factor used on the diode, BJT, JFET, and MES-
FET devices determines the number of equivalent parallel
devices of a specified model. The affected parameters are
marked with an asterisk under the heading 'area' in the
model descriptions below. Several geometric factors associ-
ated with the channel and the drain and source diffusions
can be specified on the MOSFET device line.
Two different forms of initial conditions may be speci-
fied for some devices. The first form is included to
improve the dc convergence for circuits that contain more
than one stable state. If a device is specified OFF, the dc
operating point is determined with the terminal voltages for
that device set to zero. After convergence is obtained, the
program continues to iterate to obtain the exact value for
the terminal voltages. If a circuit has more than one dc
stable state, the OFF option can be used to force the solu-
tion to correspond to a desired state. If a device is
specified OFF when in reality the device is conducting, the
program still obtains the correct solution (assuming the
solutions converge) but more iterations are required since
the program must independently converge to two separate
solutions. The .NODESET control line serves a similar pur-
pose as the OFF option. The .NODESET option is easier to
apply and is the preferred means to aid convergence.
The second form of initial conditions are specified for
use with the transient analysis. These are true 'initial
conditions' as opposed to the convergence aids above. See
the description of the .IC control line and the .TRAN con-
trol line for a detailed explanation of initial conditions.
| Junction Diodes | BJT Models | MOSFETs | MESFET Models |
| Diode Model | Junction FieldEffect Transistors | MOSFET Models | |
| Bipolar Junction Transistors | JFET Models | MESFETs |
3.4.1. Junction Diodes
General form:
DXXXXXXX N+ N- MNAME <AREA> <OFF> <IC=VD> <TEMP=T>
Examples:
DBRIDGE 2 10 DIODE1
DCLMP 3 7 DMOD 3.0 IC=0.2
N+ and N- are the positive and negative nodes, respec-
tively. MNAME is the model name, AREA is the area factor,
and OFF indicates an (optional) starting condition on the
device for dc analysis. If the area factor is omitted, a
value of 1.0 is assumed. The (optional) initial condition
specification using IC=VD is intended for use with the UIC
option on the .TRAN control line, when a transient analysis
is desired starting from other than the quiescent operating
point. The (optional) TEMP value is the temperature at
which this device is to operate, and overrides the tempera-
ture specification on the .OPTION control line.
3.4.2. Diode Model (D)
The dc characteristics of the diode are determined by
the parameters IS and N. An ohmic resistance, RS, is in-
cluded. Charge storage effects are modeled by a transit
time, TT, and a nonlinear depletion layer capacitance which
is determined by the parameters CJO, VJ, and M. The tem-
perature dependence of the saturation current is defined by
the parameters EG, the energy and XTI, the saturation
current temperature exponent. The nominal temperature at
which these parameters were measured is TNOM, which defaults
to the circuit-wide value specified on the .OPTIONS control
line. Reverse breakdown is modeled by an exponential in-
crease in the reverse diode current and is determined by the
parameters BV and IBV (both of which are positive numbers).
name parameter units default example area
1 IS saturation current A 1.0e-14 1.0e-14 *
2 RS ohmic resistance Z 0 10 *
3 N emission coefficient - 1 1.0
4 TT transit-time sec 0 0.1ns
5 CJO zero-bias junction capacitance F 0 2pF *
6 VJ junction potential V 1 0.6
7 M grading coefficient - 0.5 0.5
8 EG activation energy eV 1.11 1.11 Si
0.69 Sbd
0.67 Ge
9 XTI saturation-current temp. exp - 3.0 3.0 jn
2.0 Sbd
10 KF flicker noise coefficient - 0
11 AF flicker noise exponent - 1
12 FC coefficient for forward-bias - 0.5
depletion capacitance formula
13 BV reverse breakdown voltage V infinite 40.0
14 IBV current at breakdown voltage A 1.0e-3
o
15 TNOM parameter measurement temperature C 27 50
3.4.3. Bipolar Junction Transistors (BJTs)
General form:
QXXXXXXX NC NB NE <NS> MNAME <AREA> <OFF> <IC=VBE, VCE> <TEMP=T>
Examples:
Q23 10 24 13 QMOD IC=0.6, 5.0
Q50A 11 26 4 20 MOD1
NC, NB, and NE are the collector, base, and emitter
nodes, respectively. NS is the (optional) substrate node.
If unspecified, ground is used. MNAME is the model name,
AREA is the area factor, and OFF indicates an (optional)
initial condition on the device for the dc analysis. If the
area factor is omitted, a value of 1.0 is assumed. The
(optional) initial condition specification using IC=VBE, VCE
is intended for use with the UIC option on the .TRAN control
line, when a transient analysis is desired starting from
other than the quiescent operating point. See the .IC con-
trol line description for a better way to set transient ini-
tial conditions. The (optional) TEMP value is the tempera-
ture at which this device is to operate, and overrides the
temperature specification on the .OPTION control line.
3.4.4. BJT Models (NPN/PNP)
The bipolar junction transistor model in SPICE is an
adaptation of the integral charge control model of Gummel
and Poon. This modified Gummel-Poon model extends the ori-
ginal model to include several effects at high bias levels.
The model automatically simplifies to the simpler Ebers-Moll
model when certain parameters are not specified. The param-
eter names used in the modified Gummel-Poon model have been
chosen to be more easily understood by the program user, and
to reflect better both physical and circuit design thinking.
The dc model is defined by the parameters IS, BF, NF,
ISE, IKF, and NE which determine the forward current gain
characteristics, IS, BR, NR, ISC, IKR, and NC which deter-
mine the reverse current gain characteristics, and VAF and
VAR which determine the output conductance for forward and
reverse regions. Three ohmic resistances RB, RC, and RE are
included, where RB can be high current dependent. Base
charge storage is modeled by forward and reverse transit
times, TF and TR, the forward transit time TF being bias
dependent if desired, and nonlinear depletion layer capaci-
tances which are determined by CJE, VJE, and MJE for the B-E
junction , CJC, VJC, and MJC for the B-C junction and CJS,
VJS, and MJS for the C-S (Collector-Substrate) junction.
The temperature dependence of the saturation current, IS, is
determined by the energy-gap, EG, and the saturation current
temperature exponent, XTI. Additionally base current tem-
perature dependence is modeled by the beta temperature
exponent XTB in the new model. The values specified are
assumed to have been measured at the temperature TNOM, which
can be specified on the .OPTIONS control line or overridden
by a specification on the .MODEL line.
The BJT parameters used in the modified Gummel-Poon
model are listed below. The parameter names used in earlier
versions of SPICE2 are still accepted.
Modified Gummel-Poon BJT Parameters.
name parameter units default example area
1 IS transport saturation current A 1.0e-16 1.0e-15 *
2 BF ideal maximum forward beta - 100 100
3 NF forward current emission coefficient - 1.0 1
4 VAF forward Early voltage V infinite 200
5 IKF corner for forward beta
high current roll-off A infinite 0.01 *
6 ISE B-E leakage saturation current A 0 1.0e-13 *
7 NE B-E leakage emission coefficient - 1.5 2
8 BR ideal maximum reverse beta - 1 0.1
9 NR reverse current emission coefficient - 1 1
10 VAR reverse Early voltage V infinite 200
11 IKR corner for reverse beta
high current roll-off A infinite 0.01 *
12 ISC B-C leakage saturation current A 0 1.0e-13 *
13 NC B-C leakage emission coefficient - 2 1.5
14 RB zero bias base resistance Z 0 100 *
15 IRB current where base resistance
falls halfway to its min value A infinite 0.1 *
16 RBM minimum base resistance
at high currents Z RB 10 *
17 RE emitter resistance Z 0 1 *
18 RC collector resistance Z 0 10 *
19 CJE B-E zero-bias depletion capacitance F 0 2pF *
20 VJE B-E built-in potential V 0.75 0.6
21 MJE B-E junction exponential factor - 0.33 0.33
22 TF ideal forward transit time sec 0 0.1ns
23 XTF coefficient for bias dependence of TF - 0
24 VTF voltage describing VBC
dependence of TF V infinite
25 ITF high-current parameter
for effect on TF A 0 *
26 PTF excess phase at freq=1.0/(TF*2PI) Hz deg 0
27 CJC B-C zero-bias depletion capacitance F 0 2pF *
28 VJC B-C built-in potential V 0.75 0.5
29 MJC B-C junction exponential factor - 0.33 0.5
30 XCJC fraction of B-C depletion capacitance - 1
connected to internal base node
31 TR ideal reverse transit time sec 0 10ns
32 CJS zero-bias collector-substrate
capacitance F 0 2pF *
33 VJS substrate junction built-in potential V 0.75
34 MJS substrate junction exponential factor - 0 0.5
35 XTB forward and reverse beta
temperature exponent - 0
36 EG energy gap for temperature
effect on IS eV 1.11
37 XTI temperature exponent for effect on IS - 3
38 KF flicker-noise coefficient - 0
39 AF flicker-noise exponent - 1
40 FC coefficient for forward-bias
depletion capacitance formula - 0.5
o
41 TNOM Parameter measurement temperature C 27 50
3.4.5. Junction Field-Effect Transistors (JFETs)
General form:
JXXXXXXX ND NG NS MNAME <AREA> <OFF> <IC=VDS, VGS> <TEMP=T>
Examples:
J1 7 2 3 JM1 OFF
ND, NG, and NS are the drain, gate, and source nodes,
respectively. MNAME is the model name, AREA is the area
factor, and OFF indicates an (optional) initial condition on
the device for dc analysis. If the area factor is omitted,
a value of 1.0 is assumed. The (optional) initial condition
specification, using IC=VDS, VGS is intended for use with
the UIC option on the .TRAN control line, when a transient
analysis is desired starting from other than the quiescent
operating point. See the .IC control line for a better way
to set initial conditions. The (optional) TEMP value is the
temperature at which this device is to operate, and over-
rides the temperature specification on the .OPTION control
line.
3.4.6. JFET Models (NJF/PJF)
The JFET model is derived from the FET model of Shich-
man and Hodges. The dc characteristics are defined by the
parameters VTO and BETA, which determine the variation of
drain current with gate voltage, LAMBDA, which determines
the output conductance, and IS, the saturation current of
the two gate junctions. Two ohmic resistances, RD and RS,
are included. Charge storage is modeled by nonlinear deple-
tion layer capacitances for both gate junctions which vary
as the -1/2 power of junction voltage and are defined by the
parameters CGS, CGD, and PB.
Note that in Spice3f and later, a fitting parameter B
has been added. For details, see [9].
name parameter units default example area
1 VTO threshold voltage (V V -2.0 -2.0
TO 2
2 BETA transconductance parameter (B) A/V 1.0e-4 1.0e-3 *
3 LAMBDA channel-length modulation
parameter (L) 1/V 0 1.0e-4
4 RD drain ohmic resistance Z 0 100 *
5 RS source ohmic resistance Z 0 100 *
6 CGS zero-bias G-S junction capacitance (C ) F 0 5pF *
gs
7 CGD zero-bias G-D junction capacitance (C ) F 0 1pF *
gs
8 PB gate junction potential V 1 0.6
9 IS gate junction saturation current (I ) A 1.0e-14 1.0e-14 *
S
10 B doping tail parameter - 1 1.1
11 KF flicker noise coefficient - 0
12 AF flicker noise exponent - 1
13 FC coefficient for forward-bias - 0.5
depletion capacitance formula
o
14 TNOM parameter measurement temperature C 27 50
3.4.7. MOSFETs
General form:
MXXXXXXX ND NG NS NB MNAME <L=VAL> <W=VAL> <AD=VAL> <AS=VAL>
+ <PD=VAL> <PS=VAL> <NRD=VAL> <NRS=VAL> <OFF>
+ <IC=VDS, VGS, VBS> <TEMP=T>
Examples:
M1 24 2 0 20 TYPE1
M31 2 17 6 10 MODM L=5U W=2U
M1 2 9 3 0 MOD1 L=10U W=5U AD=100P AS=100P PD=40U PS=40U
ND, NG, NS, and NB are the drain, gate, source, and bulk
(substrate) nodes, respectively. MNAME is the model name.
L and W are the channel length and width, in meters. AD and
AS are the areas of the drain and source diffusions, in
2
meters . Note that the suffix U specifies microns (1e-6 m)
2
and P sq-microns (1e-12 m ). If any of L, W, AD, or AS are
not specified, default values are used. The use of defaults
simplifies input file preparation, as well as the editing
required if device geometries are to be changed. PD and PS
are the perimeters of the drain and source junctions, in
meters. NRD and NRS designate the equivalent number of
squares of the drain and source diffusions; these values
multiply the sheet resistance RSH specified on the .MODEL
control line for an accurate representation of the parasitic
series drain and source resistance of each transistor. PD
and PS default to 0.0 while NRD and NRS to 1.0. OFF indi-
cates an (optional) initial condition on the device for dc
analysis. The (optional) initial condition specification
using IC=VDS, VGS, VBS is intended for use with the UIC
option on the .TRAN control line, when a transient analysis
is desired starting from other than the quiescent operating
point. See the .IC control line for a better and more con-
venient way to specify transient initial conditions. The
(optional) TEMP value is the temperature at which this dev-
ice is to operate, and overrides the temperature specifica-
tion on the .OPTION control line. The temperature specifi-
cation is ONLY valid for level 1, 2, 3, and 6 MOSFETs, not
for level 4 or 5 (BSIM) devices.
3.4.8. MOSFET Models (NMOS/PMOS)
SPICE provides four MOSFET device models, which differ
in the formulation of the I-V characteristic. The variable
LEVEL specifies the model to be used:
LEVEL=1 -> Shichman-Hodges
LEVEL=2 -> MOS2 (as described in [1])
LEVEL=3 -> MOS3, a semi-empirical model(see [1])
LEVEL=4 -> BSIM (as described in [3])
LEVEL=5 -> new BSIM (BSIM2; as described in [5])
LEVEL=6 -> MOS6 (as described in [2])
The dc characteristics of the level 1 through level 3 MOS- FETs are defined by the device parameters VTO, KP, LAMBDA, PHI and GAMMA. These parameters are computed by SPICE if process parameters (NSUB, TOX, ...) are given, but user- specified values always override. VTO is positive (nega- tive) for enhancement mode and negative (positive) for depletion mode N-channel (P-channel) devices. Charge storage is modeled by three constant capacitors, CGSO, CGDO, and CGBO which represent overlap capacitances, by the non- linear thin-oxide capacitance which is distributed among the gate, source, drain, and bulk regions, and by the nonlinear depletion-layer capacitances for both substrate junctions divided into bottom and periphery, which vary as the MJ and MJSW power of junction voltage respectively, and are deter- mined by the parameters CBD, CBS, CJ, CJSW, MJ, MJSW and PB. Charge storage effects are modeled by the piecewise linear voltages-dependent capacitance model proposed by Meyer. The thin-oxide charge-storage effects are treated slightly dif- ferent for the LEVEL=1 model. These voltage-dependent capa- citances are included only if TOX is specified in the input description and they are represented using Meyer's formula- tion.
There is some overlap among the parameters describing
the junctions, e.g. the reverse current can be input either
2
as IS (in A) or as JS (in A/m ). Whereas the first is an
absolute value the second is multiplied by AD and AS to give
the reverse current of the drain and source junctions
respectively. This methodology has been chosen since there
is no sense in relating always junction characteristics with
AD and AS entered on the device line; the areas can be
defaulted. The same idea applies also to the zero-bias
junction capacitances CBD and CBS (in F) on one hand, and CJ
2
(in F/m ) on the other. The parasitic drain and source
series resistance can be expressed as either RD and RS (in
ohms) or RSH (in ohms/sq.), the latter being multiplied by
the number of squares NRD and NRS input on the device line.
A discontinuity in the MOS level 3 model with respect
to the KAPPA parameter has been detected (see [10]). The
supplied fix has been implemented in Spice3f2 and later.
Since this fix may affect parameter fitting, the option
"BADMOS3" may be set to use the old implementation (see the
section on simulation variables and the ".OPTIONS" line).
SPICE level 1, 2, 3 and 6 parameters:
name parameter units default example
1 LEVEL model index - 1
2 VTO zero-bias threshold voltage (V ) V 0.0 1.0
TO 2
3 KP transconductance parameter A/V 2.0e-5 3.1e-5
1/2
4 GAMMA bulk threshold parameter (\) V 0.0 0.37
5 PHI surface potential (U) V 0.6 0.65
6 LAMBDA channel-length modulation
(MOS1 and MOS2 only) (L) 1/V 0.0 0.02
7 RD drain ohmic resistance Z 0.0 1.0
8 RS source ohmic resistance Z 0.0 1.0
9 CBD zero-bias B-D junction capacitance F 0.0 20fF
10 CBS zero-bias B-S junction capacitance F 0.0 20fF
11 IS bulk junction saturation current (I ) A 1.0e-14 1.0e-15
S
12 PB bulk junction potential V 0.8 0.87
13 CGSO gate-source overlap capacitance
per meter channel width F/m 0.0 4.0e-11
14 CGDO gate-drain overlap capacitance
per meter channel width F/m 0.0 4.0e-11
15 CGBO gate-bulk overlap capacitance
per meter channel length F/m 0.0 2.0e-10
16 RSH drain and source diffusion
sheet resistance Z/[] 0.0 10.0
17 CJ zero-bias bulk junction bottom cap.
2
per sq-meter of junction area F/m 0.0 2.0e-4
18 MJ bulk junction bottom grading coeff. - 0.5 0.5
19 CJSW zero-bias bulk junction sidewall cap.
per meter of junction perimeter F/m 0.0 1.0e-9
20 MJSW bulk junction sidewall grading coeff. - 0.50(level1)
0.33(level2, 3)
21 JS bulk junction saturation current
2
per sq-meter of junction area A/m 1.0e-8
22 TOX oxide thickness meter 1.0e-7 1.0e-7
3
23 NSUB substrate doping 1/cm 0.0 4.0e15
2
24 NSS surface state density 1/cm 0.0 1.0e10
2
25 NFS fast surface state density 1/cm 0.0 1.0e10
continued
name parameter units default example
26 TPG type of gate material: - 1.0
+1 opp. to substrate
-1 same as substrate
0 Al gate
27 XJ metallurgical junction depth meter 0.0 1M
28 LD lateral diffusion meter 0.0 0.8M
2
29 UO surface mobility cm /Vs 600 700
30 UCRIT critical field for mobility
degradation (MOS2 only) V/cm 1.0e4 1.0e4
31 UEXP critical field exponent in
mobility degradation (MOS2 only) - 0.0 0.1
32 UTRA transverse field coeff. (mobility)
(deleted for MOS2) - 0.0 0.3
33 VMAX maximum drift velocity of carriers m/s 0.0 5.0e4
34 NEFF total channel-charge (fixed and
mobile) coefficient (MOS2 only) - 1.0 5.0
35 KF flicker noise coefficient - 0.0 1.0e-26
36 AF flicker noise exponent - 1.0 1.2
37 FC coefficient for forward-bias
depletion capacitance formula - 0.5
38 DELTA width effect on threshold voltage
(MOS2 and MOS3) - 0.0 1.0
39 THETA mobility modulation (MOS3 only) 1/V 0.0 0.1
40 ETA static feedback (MOS3 only) - 0.0 1.0
41 KAPPA saturation field factor (MOS3 only) - 0.2 0.5
o
42 TNOM parameter measurement temperature C 27 50
The level 4 and level 5 (BSIM1 and BSIM2) parameters
are all values obtained from process characterization, and
can be generated automatically. J. Pierret [4] describes a
means of generating a 'process' file, and the program
Proc2Mod provided with SPICE3 converts this file into a se-
quence of BSIM1 ".MODEL" lines suitable for inclusion in a
SPICE input file. Parameters marked below with an * in the
l/w column also have corresponding parameters with a length
and width dependency. For example, VFB is the basic parame-
ter with units of Volts, and LVFB and WVFB also exist and
have units of Volt-Mmeter The formula
P P
L W
P = P + ---------- + ----------
0
L W
effective effective
is used to evaluate the parameter for the actual device specified with
L = L - DL
effective input
and
W = W - DW
effective input
Note that unlike the other models in SPICE, the BSIM
model is designed for use with a process characterization
system that provides all the parameters, thus there are no
defaults for the parameters, and leaving one out is con-
sidered an error. For an example set of parameters and the
format of a process file, see the SPICE2 implementation
notes[3].
For more information on BSIM2, see reference [5].
SPICE BSIM (level 4) parameters.
name parameter units l/w
VFB flat-band voltage V *
PHI surface inversion potential V *
1/2
K1 body effect coefficient V *
K2 drain/source depletion charge-sharing coefficient - *
ETA zero-bias drain-induced barrier-lowering coefficient - *
2
MUZ zero-bias mobility cm /V-s
DL shortening of channel Mm
DW narrowing of channel Mm
-1
U0 zero-bias transverse-field mobility degradation coefficient V *
U1 zero-bias velocity saturation coefficient Mm/V *
2 2
X2MZ sens. of mobility to substrate bias at v =0 cm /V -s *
ds -1
X2E sens. of drain-induced barrier lowering effect to substrate bias V *
-1
X3E sens. of drain-induced barrier lowering effect to drain bias at V =V V *
ds dd -2
X2U0 sens. of transverse field mobility degradation effect to substrate bias V *
-2
X2U1 sens. of velocity saturation effect to substrate bias MmV *
2 2
MUS mobility at zero substrate bias and at V =V cm /V -s
ds dd 2 2
X2MS sens. of mobility to substrate bias at V =V cm /V -s *
ds dd 2 2
X3MS sens. of mobility to drain bias at V =V cm /V -s *
ds dd -2
X3U1 sens. of velocity saturation effect on drain bias at V =V MmV *
ds dd
TOX gate oxide thickness Mm
o
TEMP temperature at which parameters were measured C
VDD measurement bias range V
CGDO gate-drain overlap capacitance per meter channel width F/m
CGSO gate-source overlap capacitance per meter channel width F/m
CGBO gate-bulk overlap capacitance per meter channel length F/m
XPART gate-oxide capacitance-charge model flag -
N0 zero-bias subthreshold slope coefficient - *
NB sens. of subthreshold slope to substrate bias - *
ND sens. of subthreshold slope to drain bias - *
RSH drain and source diffusion sheet resistance Z/[]
2
JS source drain junction current density A/m
PB built in potential of source drain junction V
MJ Grading coefficient of source drain junction -
PBSW built in potential of source, drain junction sidewall V
MJSW grading coefficient of source drain junction sidewall -
2
CJ Source drain junction capacitance per unit area F/m
CJSW source drain junction sidewall capacitance per unit length F/m
WDF source drain junction default width m
DELL Source drain junction length reduction m
XPART = 0 selects a 40/60 drain/source charge partition
in saturation, while XPART=1 selects a 0/100 drain/source
charge partition.
ND, NG, and NS are the drain, gate, and source nodes,
respectively. MNAME is the model name, AREA is the area
factor, and OFF indicates an (optional) initial condition on
the device for dc analysis. If the area factor is omitted,
a value of 1.0 is assumed. The (optional) initial condition
specification, using IC=VDS, VGS is intended for use with
the UIC option on the .TRAN control line, when a transient
analysis is desired starting from other than the quiescent
operating point. See the .IC control line for a better way
to set initial conditions.
3.4.9. MESFETs
General form:
ZXXXXXXX ND NG NS MNAME <AREA> <OFF> <IC=VDS, VGS>
Examples:
Z1 7 2 3 ZM1 OFF
3.4.10. MESFET Models (NMF/PMF)
The MESFET model is derived from the GaAs FET model of
Statz et al. as described in [11]. The dc characteristics
are defined by the parameters VTO, B, and BETA, which deter-
mine the variation of drain current with gate voltage, AL-
PHA, which determines saturation voltage, and LAMBDA, which
determines the output conductance. The formula are given
by:
3
2
B (V -V ) | | V | | 3
gs T ds _
I = --------------- |1 - |1-A---| |(1 + L V ) for 0 < V <
d ds ds
1 + b(V - V ) | | 3 | | A
gs T
2
B (V -V ) 3
gs T _
I = ---------------(1 + L V ) for V >
d ds ds
1 + b(V - V ) A
gs T
Two ohmic resistances, RD and RS, are included. Charge
storage is modeled by total gate charge as a function of
gate-drain and gate-source voltages and is defined by the
parameters CGS, CGD, and PB.
name parameter units default example area
1 VTO pinch-off voltage V -2.0 -2.0
2
2 BETA transconductance parameter A/V 1.0e-4 1.0e-3 *
3 B doping tail extending parameter 1/V 0.3 0.3 *
4 ALPHA saturation voltage parameter 1/V 2 2 *
5 LAMBDA channel-length modulation
parameter 1/V 0 1.0e-4
6 RD drain ohmic resistance Z 0 100 *
7 RS source ohmic resistance Z 0 100 *
8 CGS zero-bias G-S junction capacitance F 0 5pF *
9 CGD zero-bias G-D junction capacitance F 0 1pF *
10 PB gate junction potential V 1 0.6
11 KF flicker noise coefficient - 0
12 AF flicker noise exponent - 1
13 FC coefficient for forward-bias - 0.5
depletion capacitance formula
4. ANALYSES AND OUTPUT CONTROL
The following command lines are for specifying analyses
or plots within the circuit description file. Parallel com-
mands exist in the interactive command interpreter (detailed
in the following section). Specifying analyses and plots
(or tables) in the input file is useful for batch runs.
Batch mode is entered when either the -b option is given or
when the default input source is redirected from a file. In
batch mode, the analyses specified by the control lines in
the input file (e.g. ".ac", ".tran", etc.) are immediately
executed (unless ".control" lines exists; see the section on
the interactive command interpretor). If the -r rawfile
option is given then all data generated is written to a
Spice3 rawfile. The rawfile may be read by either the
interactive mode of Spice3 or by nutmeg; see the previous
section for details. In this case, the .SAVE line (see
below) may be used to record the value of internal device
variables (see Appendix B).
If a rawfile is not specified, then output plots (in
"line-printer" form) and tables can be printed according to
the .PRINT, .PLOT, and .FOUR control lines, described next.
.PLOT, .PRINT, and .FOUR lines are meant for compatibility
with Spice2.
| SIMULATOR VARIABLES | INITIAL CONDITIONS | ANALYSES | BATCH OUTPUT |
4.1. SIMULATOR VARIABLES (.OPTIONS)
Various parameters of the simulations available in
Spice3 can be altered to control the accuracy, speed, or
default values for some devices. These parameters may be
changed via the "set" command (described later in the sec-
tion on the interactive front-end) or via the ".OPTIONS"
line:
General form:
.OPTIONS OPT1 OPT2 ... (or OPT=OPTVAL ...)
Examples:
.OPTIONS RELTOL=.005 TRTOL=8
The options line allows the user to reset program con-
trol and user options for specific simulation purposes.
Additional options for Nutmeg may be specified as well and
take effect when Nutmeg reads the input file. Options
specified to Nutmeg via the 'set' command are also passed on
to SPICE3 as if specified on a .OPTIONS line. See the fol-
lowing section on the interactive command interpreter for
the parameters which may be set with a .OPTIONS line and the
format of the 'set' command. Any combination of the follow-
ing options may be included, in any order. 'x' (below)
represents some positive number.
option effect
ABSTOL=x resets the absolute current error tolerance of the
program.
The default value is 1 picoamp.
BADMOS3 Use the older version of the MOS3 model with the "kappa"
discontinuity.
CHGTOL=x resets the charge tolerance of the program. The default
value is 1.0e-14.
DEFAD=x resets the value for MOS drain diffusion area; the
default is 0.0.
DEFAS=x resets the value for MOS source diffusion area; the
default is 0.0.
DEFL=x resets the value for MOS channel length; the default
is 100.0 micrometer.
DEFW=x resets the value for MOS channel width; the default
is 100.0 micrometer.
GMIN=x resets the value of GMIN, the minimum conductance
allowed by the program.
The default value is 1.0e-12.
ITL1=x resets the dc iteration limit. The default is 100.
ITL2=x resets the dc transfer curve iteration limit. The
default is 50.
ITL3=x resets the lower transient analysis iteration limit.
the default value is 4. (Note: not implemented in Spice3).
ITL4=x resets the transient analysis timepoint iteration limit.
the default is 10.
ITL5=x resets the transient analysis total iteration limit.
the default is 5000. Set ITL5=0 to omit this test.
(Note: not implemented in Spice3).
KEEPOPINFO Retain the operating point information when either an
AC, Distortion, or Pole-Zero analysis is run.
This is particularly useful if the circuit is large
and you do not want to run a (redundant) ".OP" analysis.
METHOD=name sets the numerical integration method used by SPICE.
Possible names are "Gear" or "trapezoidal" (or just "trap").
The default is trapezoidal.
PIVREL=x resets the relative ratio between the largest column entry
and an acceptable pivot value. The default value is 1.0e-3.
In the numerical pivoting algorithm the allowed minimum
pivot value is determined by
EPSREL=AMAX1(PIVREL*MAXVAL, PIVTOL)
where MAXVAL is the maximum element in the column where
a pivot is sought (partial pivoting).
PIVTOL=x resets the absolute minimum value for a matrix entry
to be accepted as a pivot. The default value is 1.0e-13.
RELTOL=x resets the relative error tolerance of the program.
The
default value is 0.001 (0.1%).
TEMP=x Resets the operating temperature of the circuit. The
default value is 27 deg C (300 deg K). TEMP can be overridden
by a temperature specification on any temperature dependent
instance.
TNOM=x resets the nominal temperature at which device parameters
are measured. The default value is 27 deg C (300 deg K).
TNOM can be overridden by a specification on any temperature
dependent device model.
TRTOL=x resets the transient error tolerance. The default value
is 7.0. This parameter is an estimate of the factor by
which SPICE overestimates the actual truncation error.
TRYTOCOMPACT Applicable only to the LTRA model.
When specified, the simulator tries to condense LTRA transmission
lines' past history of input voltages and currents.
VNTOL=x resets the absolute voltage error tolerance of the
program. The default value is 1 microvolt.
In addition, the following options have the listed
effect when operating in spice2 emulation mode:
option effect
option effect ACCT causes accounting and run time statistics to be printed LIST causes the summary listing of the input data to be printed NOMOD suppresses the printout of the model parameters NOPAGE suppresses page ejects NODE causes the printing of the node table. OPTS causes the option values to be printed.
4.2. INITIAL CONDITIONS
| .NODESET | .IC |
4.2.1. .NODESET: Specify Initial Node Voltage Guesses